ISE: Map failed due to timing can not meet

在用ISE Implement Design的时候，在Map阶段就由于timing的问题fail了。Error信息如下：
Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary will appear in the map report. This summary will show a MINIMUM net delay for the paths. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual. For more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter.

由于在Map阶段，还没有考虑wire delay而只有cell delay，所以这个时候timing无法满足是必须要解决的。问题是fail以后，无法生成STA report，这样也就无法确定是哪条path出了问题。解决方法是：设置环境变量set XIL_TIMING_ALLOW_IMPOSSIBLE=1，让ISE在impossible的情况下仍然继续下去。这样可以生成STA report，我们就可以定位critical path并给出相应的解决方法了。