1. Move critical signal close to output of a gate, this may be used in ECO phase.
2. Move critical signal closer to the output
3. Replicate logic
4. Use Complex Gate
4. Use Complex Gate
5. Retiming – move logic to next T
6. Retiming - move Logic to prev T
7. Clock Gating
8. Additional methods
1)Use Low Vt cell to improve timing
1)Use Low Vt cell to improve timing
2)Size up weak gates in the path
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