Avoid Using Clock Gating In FPGA Emulation

For power saving consideration, clock gating is used in ASIC design. EDA tools are used to balance clocks which come from the same source clock and only the enable signals are different. But in FPGA design, no balance is done among related clocks. The skew among related clocks may be larger or smaller which can not be forecast. This may lead to unexpected results.
Besides, there is no AND/OR/LATCH… etc. only LUT/FF/BUF in FPGA.