Xilinx/Virtex-5 DCM problem:the minimum frequence of input clock

I have an input clock of 24MHz and I need to get a 48MHz clock using DCM. During PAR, there were the following warnings:
WARNING:Timing:3325 - Timing Constraint
"TS_CLK24 = PERIOD TIMEGRP "CLK24" 42 ns HIGH 50%;"
fails the maximum period check for input clock clk48_gen/CLKIN_IBUFG_OUT to DCM_ADV clk48_gen_DCM_INST because the period constraint value (42000 ps) exceeds the maximum internal period limit of 31251 ps.Please reduce the period of the constraint to remove this timing failure.
...

That means the minimum input clock of the DCM is about 32MHz (10^6/31251ps=31.998976MHz) while my input clock is only 24MHz. I did not know whether this DCM will operate normally or not. I think the intuitional way is that:output this 48MHz signal/clock and observe it on LAs. My FPGA board will be ready in several days. I will test and then update this blog.

The following is someone's explanation I found in Xilinx/Forum:
These warnings usually indicate that the period constraint specified in your design violates one of the Spec'ed operating ranges in the datasheet for that device (ie, faster than the Max Frequency of a DCM, etc.). This doesn't necessarily mean that it won't work, but it does mean that it's outside of the range that Xilinx has tested and guarantees. You might take a look in the datasheet for the device you're targetting to see if the frequency you're requesting is outside of the range for either it's driver or load.